To provide reduced power consumption in the dynamic random access memory (DRAM) devices for the mobile market, various low power double data rate (LPDDR) DRAM standards have evolved in which the DRAM may vary the signaling voltage and data rate used to receive data from a transmitting device such as a system-on-a-chip (SoC). A communication channel extends between the SoC and the DRAM over which each bit is transmitted as either a binary high (logic one) symbol or a binary low (logic zero) symbol over the symbol interval. Each DRAM can selectively terminate (present a matched load) or non-terminate with regard to the communication channel. If a DRAM does not terminate, the input impedance to the DRAM is mismatched to the characteristic impedance of the communication channel. Conversely, if a DRAM does terminate, its input impedance is matched to the characteristic impedance of the communication channel.
The mismatched input impedance for a DRAM in a non-terminated mode of operation causes the data transmitted from the SoC to reflect back to the SoC. Such reflections are generally deemed to be undesirable such that it is conventional for the DRAM to active its termination during a high-speed data transmission mode. During a low-speed mode of operation, the DRAM may then deactivate its termination to save power since the matched load (e.g., a 50 ohm resistor) dissipates power to ground. Such termination is commonly implemented in multi-rank architectures in which the SOC couples to a plurality of DRAMs through a common communication channel. The common communication channel ends in one or more bifurcations so that each DRAM can couple to the common communication channel.
In a multi-rank memory bus architecture, the SoC writes to one DRAM at a time such that there is an active (being written to) DRAM and one or more inactive DRAMs (not being written to). In a high-speed mode of operation, it is conventional for the active DRAM to be terminated while the inactive DRAMs are non-terminated. But as data rates are increased higher and higher, it is becoming more difficult to maintain a sufficient data eye at the active DRAM.
Accordingly, there is a need in the art for improved termination schemes for multi-rank memory bus architectures.